Q&A with Kaushal Pathak – Mentor R&D
In this interview I ask Kaushal Pathak of the Questa Formal GUI R&D team about the contrasting considerations for formal-centric vs. simulation-centric interaction design, as well as reconciling the competing requirements for making novice and expert formal users’ work-flows efficient and effective.
Q&A with Steve Geisler – Mentor R&D
In this interview I ask Steve Geisler of the Questa Formal GUI R&D team about the challenges in migrating from the legacy Tcl/Tk GUI platform to the state-of-the-art Qt GUI technology, and how Qt enables efficient design of scalable, interactive GUI work-flows for formal analysis.
Q&A with Hirak Roy – Mentor R&D
In this interview I ask Hirak Roy of the Questa Formal team about how Mentor’s PropCheck formal tool efficiently maps its engines to the customer’s available compute resources, how the algorithm orchestration architecture gives users predictable, linear scalability of compute resource consumption, and how compute resources can be freed up on-the-fly as the properties are proven over the course of the formal analysis.
Stuck on a Desert Island without Simulation – Only Formal!
It could happen to any of us: your plane is stricken by mechanical failure and is forced on a desert island. Your only hope of rescue is to verify the RTL for a solar powered drone that will fly to the nearest civilization with your message. All you have for your EDA usage is a solar powered Linux laptop, your DUT’s RTL, some planning & management tools, and formal & CDC apps — no simulation!
In this video I introduce the above premise to the audience, then go on into a technical outline of how to translate verification requirements for the drone’s controller into a machine-readable verification plan and related coverage goals.
Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs
In this interview the presenters of the DVCon USA 2016 tutorial, “Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs” talk about the latest advances in low power design&verification introduced in the UPF 3.0 standard, and how it enables bit IP creators and IP customers to simplify their D&V flows. (Featuring: Gabriel Chidolue, Jonathan Lovett, and Shantanu Samant)
Back to the Basics: Doing Formal The Right Way
In this interview the presenters of the DVCon USA 2016 tutorial, “Back to Basics: Doing Formal ‘The Right Way’” describe how D&V engineers can gradually adopt formal — enjoying correspondingly greater quality and schedule benefits starting automated formal apps through advanced property checking methodologies. (Featuring Doug Smith and Mark Eslinger)
Interview of Jeremy Levitt about his “Instant Formal Expert” Verification Academy talk
Join me as I interview R&D’s Jeremy Levitt about his Verification Academy DAC Booth Theater session entitled, “Instant Formal Expert“
How Secure is Your System?
Recorded live in the DAC 2015 Verification Academy booth on June 10, 2015: Whether it’s a private encryption key for mobile payments, a milaero communications system, or a patient’s therapeutic parameters; verification of hardware access to secure storage elements is a challenging and critical task. For safety critical systems in addition to risks from external hacking, designers must ensure unexpected side-effects or bugs cannot inadvertently corrupt critical data. This session will discuss how the Secure Check app can be the foundation of your “root of trust”.
https://verificationacademy.com/sessions/dac-2015/How-Secure-is-Your-System
Harry Foster Interview on My Talk, “How Secure is Your System?”
Join Harry Foster as Yours Truly describes my Verification Academy DAC 2015 Booth Theater session entitled, “How Secure is Your System?“
Interview with Vigyan Signhal, CEO of OSKI Technology
In the past several years formal apps have introduced formal verification technologies to a whole new cohort of D&V engineers. The success of these apps have shown people the power of formal first-hand, and thus there is a marked increase in curiosity about applying formal property checking directly. In this video, I interview Oski Technology’s CEO Vigyan Singhal — a recognized expert in teaching and deploying formal analysis — about his recent Electronic Design Online article “These Five Principals Define Formal Verification“. This article — and the interview — speaks to engineers at the start of the journey from apps to direct formal analysis, and the positive surprises they can expect to encounter along the way.
Article link: http://electronicdesign.com/eda/these-five-principles-define-formal-verification
Formal Verification at DVCon US 2015
In this video interview I outline the formal verification-related activities at DVCon USA 2015. Additionally, I describe the tutorial on how a mix of formal apps and methodology can be applied to characterize acceptable and unacceptable dead DUT RTL code, quickly show how to hit uncovered DUT states, and to reach overall coverage closure faster.
Justify Your Trip to DAC
In this video interview I ask the Design Automation Conference (DAC) Designer Track chair Dan Bourke about how you can justify to yourself — let alone your boss — why you should attend DAC in San Francisco, CA this coming June 7-11
Formal Will Dominate Verification — Here’s Why
Formal analysis provides exhaustive results for any problem it’s applied to, so wouldn’t it be great if the many uncertainties around the completeness of verification could eventually be eliminated with this powerful technology? In this post I cite examples of customers who are taking big steps in this direction by using formal to completely replace simulation for many block, unit, and even system-level verification applications.
DVCon 2014 interview: NVIDIA’s Syed Suhaib reviews his paper on clock gating verification with Jasper’s SEC App
In this video I interview NVIDIA’s Syed Suhaib, who recounts his DVCon 2014 paper, “A Formal Verification App Towards Efficient, Chip-Wide Clock Gating Verification”. In a nutshell, ensuring correct clock gating has been a major verification challenge. Here Suhaib describes the automated methodology for exhaustive clock-gating verification using Sequential Equivalency Checking (SEC) analysis with Jasper’s SEC formal verification “App”. With this approach they found multiple bugs across many projects, where over half of the bugs were found after supposedly high simulation coverage of the design.
Interview about DVCon 2014 tutorial “Formally Verifying Security Aspects of SoC Designs”
In this interview I speak with Jasper’s VP of WW Application Engineering Lawrence Loh and Security Verification Specialist Victor Markus Purri about their DVCon 2014 tutorial on using formal technology to verify the secure hardware. In a nutshell, while securing software is clearly important, if the hardware foundation isn’t secure,nothing built on top of the hardware will be secure. With formal technology and methodology created by Jasper, Lawrence and Victor explain how engineers can exhaustively verify that secure data can’t be read illegally, can’t be overwritten illegally, and also remains secure in the face of faults or failure.
2013 Jasper User Group highlights
I had the great privilege of producing, writing, and directing this overview of my company’s annual user group meeting. As you can see, the event itself was very content rich, and a great opportunity for engineers to network with others.
2013 ARM TechCon Interview on Formally Verifying AMBA® 4 ACE and AMBA 5 CHI Cache-Coherent Designs
In this interview I ask senior engineer Scott Meeth about formally verifying cache-coherent interconnect designs using the AMBA® 4 ACE and AMBA 5 CHI protocols. The paper cited in the video (which I edited) can be found in the ARM Techcon 2013 proceedings as follows: Methods and Verification IP for Formally Verifying AMBA® 4 ACE and AMBA 5 CHI Cache-Coherent Designs Session Code: ATC-100, Presented Tuesday October 29 Presenter: Scott Meeth, Jasper Design Automation Authors: Scott Meeth, Dave Spatafore, and Ross Weber of Jasper Design Automation; Kath Topping, ARM
Why Are Jasper’s Formal Apps and Core Technologies Making This Bell Ring?
Why is formal verification technology in general, and Jasper’s formal apps in specific, making a classic silver bell ring? I offer some possible explanations in this video blog.
Interview with a Professional Teenage Technology Coach
Over the past several years at various EDA trade events, one of the more popular forums have been panel discussions and interviews asking teenagers about the technology in their daily lives. However, those forums have been comprised of amateurs, whereas in this interview I’ve secured a professional technology consultant — Ms. Kristine Bonhoff, a college student by day, and a paid technical coach and volunteer in her spare time. Specifically, people of a certain age pay Kristine to coach them on how to get the most out of the various gadgets and related apps they own. She also volunteers to give tech training courses to inner city residents. In this interview, Kristine shares her clients most common FAQs, their biggest positive and negative misconceptions about various technologies, and her wish list for the future.
Interview with Dr. Kerstin Eder about her course on functional verification
Dr. Kerstin Eder, Sr. Lecturer in the Computer Science department at the University of Bristol, UK teaches a course on functional verification. In this interview she outlines how the course is structured, what makes for a good verification engineer, and anecdotes of how students are getting snapped up by industry immediately after graduation. (Confirming what I see here in the USA and other geographies, if you are an engineer or computer scientist in need of a job, earning your way through courses/training like that offered by Dr. Eder will give you a leg up in this tough economy — the verification field is about as recession proof as it gets in the technology business.)
Reference link: Dr. Eder’s home page: https://research-information.bris.ac.uk/en/persons/kerstin-i-eder
“Drive For Innovation” Finds It At Every Turn
With some notable exceptions, too often technology trade press reporting has been as dour as the general world news. However, to EETimes editor Brian Fuller this negativity was at odds with the inspiring technological advances that were regularly crossing his assignments desk. In a nutshell, Brian’s confusion over this dichotomy was the seed crystal behind the “Drive for Innovation” — a partnership between Avnet Express and UBM Electronics/EETimes — and take a road trip across America in a Chevy Volt to find out the truth first-hand. In this video, shot 2/3 of the way into this yearlong adventure, Brian elaborates on his mission, and shares what he’s learned so far.
Joe Hupcey III 